Nanostructures such as Nanowires (NWs) and Carbon Nanotubes (CNTs) have been identified as one of the most promising candidates to extend and even replace materials currently used in microelectronic manufacturing processes. For example, metallic CNTs have been proposed as nano-electronic interconnects due to their high current carrying capacity, whereas semiconducting CNTs have been indicated as nanoscale transistor elements due to their large range band gap. These and similar applications cannot be fully accomplished yet since the fabrication of nanostructures still faces a variety of unsolved issues, which vary from one application to another but may, however, be similar in some aspects.
A first issue is related to the growth of nanostructures in a direction substantially parallel to a main surface of a substrate, i.e. in a direction, when the main surface of the substrate is lying in a plane, substantially parallel to the plane of the main substrate.
It would be advantageous to form catalytic nanoparticles on sidewalls of e.g. vias and/or trenches and/or any desired three-dimensional structure, and then grow nanostructures directly from these catalytic nanoparticles and thus having e.g. CNT “interconnects” already in place, instead of going through a difficult task of placing them in the desired position in a separate step. In prior art methods, placement of catalyst particles on sidewalls of three-dimensional structures is described using physical vapor deposition or chemical vapor deposition (PVD or CVD) techniques. The samples on which CNTs have to be grown are therefore placed in a reactor such that CNTs grow parallel to the wafer surface.
In “Advanced Materials, Vol. 15, No. 13, page 1105, 2003”, Cao et al. describe direction-selective in-plane growth of CNTs between pre-patterned electrodes using chemical vapor deposition techniques. This technique is however based on a shadowing effect and deposition occurs only on sidewalls which all face the same direction. Hence, with this method, CNTs can only be grown into one, predetermined direction. Hence, this technique is not suitable for, for example, interconnect applications where the connections need to go in all possible directions in a plane substantially parallel to a main surface of a substrate.
In “Applied Physics Letters, 89, 083105, 2006”, Shi et al. describe direct synthesis of single-walled CNTs by bridging metal electrodes by laser-assisted chemical vapor deposition (LCVD). However, this synthesis is very localized and restricted by the size of a laser spot used. By using this technique, only a few CNTs are created across the electrodes (FIG. 2 in this document only shows two CNTs formed on the substrate). Forming more CNTs, or in other words providing a higher density of CNTs on the substrate would be very cost-and time-ineffective because for this purpose the laser spot would have to be moved over the whole surface of the substrate. This technique is thus not well suited to obtain a high density of CNTs or NWs, e.g. a density of higher than 1012 cm−2, needed for interconnect applications. The technique is therefore not suitable for being used for mass production of CNTs.
Another issue is that the existing methods of manufacturing the above-mentioned nanostructures are not particularly compatible with standard, existing semiconductor processing techniques.
In “Advanced Materials, Vol. 12, No. 12, page 890, 2000”, Franklin et al. describe an enhanced CVD approach for extensive nanotube networks with directionality. With directionality is meant here, growing nanotubes having their longitudinal axis in a predetermined direction. However, in this approach use is made of silicon towers that are 10 μm high and it is difficult to make the method compatible with or to incorporate it in state of the art semiconductor processing.
Despite the improvements achieved up till now, selective placement of catalytic nanoparticles onto sidewalls of three-dimensional structures remains critical to obtain subsequent growth of nanostructures which may be oriented parallel to the substrate. Up till now no methods exists in such a way that they are scalable and fully compatible with existing semiconductor processing in an economical attractive and realistic way.